1. Field
One or more embodiments described herein relate to a method of detecting erase fail word-line in a non-volatile memory device.
2. Description of the Related Art
In order to improve integration, semiconductor memory devices have been developed to have a three-dimensional structure. When the number of program/erase operations in a three-dimensional memory device increases, electrons may be trapped in a memory cell or a specific word-line may rapidly deteriorate. As a result, the threshold voltage of a memory cell may not sufficiently decrease, even during an erase operation. Also, a memory cell with a high threshold voltage may be passed in an erase verify operation. This is because the memory cell has comparatively less resistance elements than other memory cells in a cell string. Consequently, the erase verify operation may be processed as an erase pass, which may adversely affect performance.